#3954 Breadboard a 4-Bit Computer
#3954 Breadboard a 4-Bit Computer
#3954 I want to breadboard a 4-bit computer. 16 commands and 4-bit address space. Describe what I will need.
This is a classic project, often referred to as the SAP-1 (Simple As Possible) architecture. The constraints you listed (16 commands, 4-bit address space) fit perfectly into an 8-bit instruction word structure: the upper 4 bits define the Opcode (16 commands), and the lower 4 bits define the Operand (the memory address).
Even though the instruction word is 8 bits wide, the computational core (ALU) and registers can be kept to 4 bits to satisfy your "4-bit computer" goal.
Here is the breakdown of the hardware, logic, and architecture you will need.
1. The Core Architecture (The "Mental" Breadboard)
You are building a bus-based architecture. All components connect to a central data highway (The Bus).
The Bus: 8-bits wide (to carry instruction + address in one go).
ALU (Arithmetic Logic Unit): 4-bit (performs math).
RAM: 16 Bytes (2^4 address space).
Control Unit: Decodes the 4-bit opcodes into control signals.
2. Bill of Materials (BOM)
We will use the 74LS (Low-power Schottky) series of logic chips. They are robust, handle 5V power well, and are the standard for breadboard computers.
A. Infrastructure
Breadboards: 4 to 6 large logic breadboards (830 tie-points).
Power Supply: A dedicated 5V bench supply or a high-quality USB breakout (don't rely on cheap batteries; logic chips are power-hungry).
Wire: 22 AWG solid core wire (get multiple colors to color-code your data bus vs. control lines).
LEDs: ~40 (for debugging the bus, registers, and flags).
Resistors: 220Ω (for LEDs) and 1kΩ/10kΩ (for pull-up/down).
B. The Clock Module
This drives the speed of the computer. You need three modes: Astables (running fast), Monostable (manual step button), and a selector.
2x NE555 Timers (or one 556).
Logic: Basic gates (AND/OR) to switch between auto and manual pulse.
C. Registers (A, B, Instruction, Output)
These store data temporarily. You need chips that have "Load" and "Output Enable" pins.
3x 74LS173: 4-bit D-type registers with 3-state outputs. (Used for Register A, Register B).
1x 74LS273: Octal D-type flip-flop (Used for the Instruction Register, as it needs to hold all 8 bits: Opcode + Operand).
D. The ALU (Math)
For a 4-bit computer, you need a 4-bit adder.
1x 74LS283: 4-bit Binary Adder.
1x 74LS86: Quad XOR gate. (You use this to invert the B-input bits to perform subtraction).
E. Memory (RAM)
You need 16 addresses.
1x 74LS189: 64-bit Random Access Memory (organized as 16 words x 4 bits).
Note: The 74LS189 outputs inverted data. You will need 74LS04 (Hex Inverters) to flip the data back to normal before putting it on the bus.
F. Program Counter (PC)
Tracks which line of code you are on.
1x 74LS161: 4-bit Binary Counter (Presettable). This counts from 0 to 15 (0000 to 1111).
G. Bus Transceivers
Crucial for controlling "who is talking" on the bus.
74LS245: Octal Bus Transceiver. Used to isolate modules from the bus until the Control Unit says "Output Now."
3. The Control Unit (The Hardest Part)
This is the conductor. It reads the 4-bit Opcode and turns on/off the correct pins on the other chips (e.g., "Load Register A", "Increment PC").
Option A: Pure Logic (The "Hard" Way)
You use dozens of AND/NAND gates to decode binary patterns.
Needs: Many 74LS08 (AND), 74LS32 (OR), 74LS04 (NOT) chips.
Option B: Microcode (The Smart Way - Recommended)
You use EEPROMs (Electrically Erasable Programmable Read-Only Memory). You program the chip once with a "lookup table." The address lines go in (Opcode + Step Counter), and the data lines go out (Control Signals).
2x AT28C16 (or AT28C64): Parallel EEPROMs.
1x 74LS138: 3-to-8 line decoder (to drive the "step" counter for the microcode).
4. Summary of Architecture Flow
To execute one of your 16 commands, your computer will cycle through Fetch, Decode, Execute:
Fetch:
PC value moves to the Memory Address Register.
RAM outputs the data at that address.
Data moves to the Instruction Register.
Decode:
The Instruction Register splits: The top 4 bits (Opcode) go to the Control Unit. The bottom 4 bits (Address) stay ready for the bus.
Execute:
The Control Unit (EEPROM) sees the Opcode and triggers the specific control lines (e.g., "Enable ALU Output", "Load Register A") to perform the math or movement.
What is your next step?
Do you want to start by designing the Instruction Set (defining what your 16 commands actually do), or would you prefer a schematic for the Clock Module to get the physical build started?
Instruction Set
Designing an instruction set for a 4-bit computer (with an 8-bit bus) requires a balance between utility and hardware complexity. Since you have a 4-bit Opcode, you have exactly 16 slots (0000 to 1111).
Here is a robust, standard instruction set based on the SAP-1 architecture, optimized to give you a Turing-complete experience.
1. The Instruction Format
Every line of code in your computer will be 8 bits wide:
Upper 4 Bits (Opcode): What action to perform (e.g., ADD, LOAD).
Lower 4 Bits (Operand): The target memory address (0-15) or a raw number (immediate value).
2. The Command Table (0x0 - 0xF)
| Opcode (Bin) | Mnemonic | Name | Description |
| 0000 | NOP | No Operation | Do nothing. Useful for delays or overwriting bad code. |
| 0001 | LDA | Load A | Load data from RAM address into Register A. |
| 0010 | ADD | Add | Add data from RAM address to Register A. Result in A. |
| 0011 | SUB | Subtract | Subtract data from RAM address from Register A. Result in A. |
| 0100 | STA | Store A | Store the value in Register A into RAM address. |
| 0101 | LDI | Load Immediate | Load the lower 4 bits of this instruction directly into A. |
| 0110 | JMP | Jump | Set Program Counter to the address in the lower 4 bits. |
| 0111 | JC | Jump if Carry | Jump only if the Carry Flag is on (result > 15). |
| 1000 | JZ | Jump if Zero | Jump only if the Zero Flag is on (result == 0). |
| 1001 | AND | Logical AND | Perform bitwise AND between A and RAM. (Requires extra HW) |
| 1010 | OR | Logical OR | Perform bitwise OR between A and RAM. (Requires extra HW) |
| 1011 | XOR | Logical XOR | Perform bitwise XOR between A and RAM. (Requires extra HW) |
| 1100 | --- | Reserved | Available for custom expansion (e.g., Shift Left). |
| 1101 | --- | Reserved | Available for custom expansion. |
| 1110 | OUT | Output | Copy Register A to the Output Register (Display). |
| 1111 | HLT | Halt | Stop the clock. The computer freezes. |
3. Key Concepts for Implementation
A. The "Immediate" Instruction (LDI)
Standard SAP-1 computers often miss this, but it is vital.
Without LDI: To load the number "5" into Register A, you must put "5" in a RAM slot, then
LDAthat RAM slot.With LDI: You just write
LDI 5(Binary:0101 0101). The computer grabs the lower 4 bits of the instruction register and moves them to the bus.
B. The Flags (Needed for JC and JZ)
To make the computer capable of logic (if/then statements), you need a Flags Register.
Carry Flag (C): Connects to the "Carry Out" pin of your 74LS283 Adder. If a math result exceeds 1111 (15), this bit flips high.
Zero Flag (Z): Use NOR gates connected to the 4 output bits of the ALU. If all bits are 0, the NOR gate outputs a 1.
Wiring: These flags connect to your Control Logic. When
JCis called, the Control Unit checks the Carry Flag wire. If high, it activates the "Jump" signal; if low, it does nothing.
C. Hardware Implications
Basic Build:
NOP,LDA,ADD,SUB,STA,LDI,JMP,OUT,HLT. (9 Commands).Advanced Build:
AND,OR,XOR. These require adding 74LS08, 74LS32, and 74LS86 chips to your ALU, plus a way to select which result goes to the bus. If you are breadboarding, you might run out of space, so many builders leave these out initially.
4. Example Program: "Count by 3s"
Here is how this instruction set looks in a real program (stored in RAM):
Address 0:
LDI 0(Initialize A to 0)Address 1:
STA 15(Store 0 into variable 'Count' at RAM slot 15)Address 2:
LDI 3(Load 3 into A)Address 3:
ADD 15(Add 'Count' to A. A is now 0+3=3)Address 4:
OUT(Display 3)Address 5:
STA 15(Save new total to 'Count')Address 6:
JMP 2(Jump back to start of loop)
What is your next step?
Now that you have the definitions, we need to wire the "brain" that enforces them. Would you like to map out the Control Signals (the microcode) for these instructions, or work on the ALU schematic to handle the math?
Map out the Control Signals
Mapping out the control signals is the "programming" of your hardware. You are defining exactly which pins go high or low at each tick of the clock to move data around.
1. The Signal Glossary (The "Alphabet")
These are the physical wires coming out of your Control Unit.
Active Low (overline X): These signals must be connected to Ground (0V) to activate. (Most 74LS chips use this).
Active High (X): These signals must be connected to 5V to activate.
| Signal | Active | Description | Target Chip Pin |
| HLT | High | Halt the clock | 555 Timer (Enable) |
| MI | Low | Memory Address Register In | 74LS173 (Load) |
| RI | Low | RAM In (Write) | 74LS189 (WE) |
| RO | Low | RAM Out (Read) | 74LS189 (CS/OE) |
| IO | Low | Instruction Register Out (To Bus) | 74LS245 (Enable) |
| II | Low | Instruction Register In | 74LS273 (Clock*) |
| AI | Low | Register A In | 74LS173 (Load) |
| AO | Low | Register A Out | 74LS173 (OE) |
| SO | Low | Sum Out (ALU result to Bus) | 74LS245 (Enable) |
| SU | High | Subtract Mode | 74LS283 (Carry In) + XORs |
| BI | Low | Register B In | 74LS173 (Load) |
| OI | Low | Output Register In | 74LS173 (Load) |
| CE | High | Counter Enable (Count Up) | 74LS161 (Enable) |
| CO | Low | Counter Out (To Bus) | 74LS245 (Enable) |
| J | Low | Jump (Load Counter) | 74LS161 (Load) |
| FI | Low | Flags In (Save Status) | 74LS173 (Load) |
*Note: Some chips latch on the rising edge (Clock), others on the level (Load). For breadboarding, we usually gate the clock with the control signal.
2. The "Fetch" Cycle (Steps T0 - T2)
Every single instruction starts with these 3 steps. The computer must fetch the instruction from RAM before it knows what to do.
T0 (Address State): Move PC value to MAR.
Signals:
CO(Counter Out),MI(MAR In)
T1 (Increment State): Increment the PC so it's ready for the next line.
Signals:
CE(Count Enable)
T2 (Memory State): Move RAM data (the instruction) to the Instruction Register.
Signals:
RO(RAM Out),II(Instruction In)
3. The "Execute" Cycle (Steps T3 - T5)
Once the instruction is in the IR, the Control Unit "wakes up" and activates specific lines based on the Opcode.
A. Data Movement
LDA (Load A from Memory)
T3:
IO(IR lower 4 bits out),MI(MAR In). Set address to read.T4:
RO(RAM Out),AI(A In). Move data to A.T5: (No Operation / Reset Step Counter)
LDI (Load Immediate)
T3:
IO(IR lower 4 bits out),AI(A In). Move instruction operand directly to A.T4: (Reset)
STA (Store A to Memory)
T3:
IO,MI. Set address to write to.T4:
AO(A Out),RI(RAM Write). Move A to RAM.T5: (Reset)
B. Arithmetic
ADD (A = A + Memory)
T3:
IO,MI. Set address to read.T4:
RO,BI. Load RAM data into Register B.T5:
SO(Sum Out),AI(A In),FI(Flags In). ALU Result -> A. Save Flags.
SUB (A = A - Memory)
T3:
IO,MI.T4:
RO,BI.T5:
SO,AI,SU(Subtract active),FI.
C. Flow Control
JMP (Unconditional Jump)
T3:
IO,J(Jump). Load the lower 4 bits of IR directly into the PC.
JC (Jump if Carry)
T3:
IO,J.Note: The
Jsignal here is special. In hardware, you wire theJcontrol line into an AND gate with the Carry Flag. If the Carry Flag is 0, theJsignal is blocked, and the PC does not load (instruction ignored).
OUT (Output)
T3:
AO,OI. Move A to Output Register.
4. How to Build the "Brain" (Implementation)
You have two main ways to physically implement this map.
Option A: The EEPROM Method (Recommended)
You burn this logic into a memory chip.
Inputs (Address Lines): The Opcode (4 bits) + Step Counter (3 bits) + Flags (2 bits).
Outputs (Data Lines): The Control Signals (active low/high).
Why: If you make a mistake in your logic, you just reprogram the chip. No rewiring 500 cables.
Option B: The Diode Matrix / Logic Gate Method
You use AND gates and inverters.
You decode the step counter (T0-T5) and the Opcode.
Example logic for MI (MAR In):
MI = (T0) \lor (LDA \land T3) \lor (ADD \land T3) dotsWhy: It looks incredibly cool and retro, but it is a nightmare to debug.
Next Step
Since you have the instruction set and the control map, do you want to design the EEPROM data structure (coding the microcode), or would you like to start breadboarding the Clock Module to get the heart beating?
From <https://gemini.google.com/app/f2e9b08f0d04b7ad> Google Gemini 3.0 Pro (Thinking)
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