#4619 Reducing Compute and Energy Needs of AI
#4619 Reducing Compute and Energy Needs of AI
#4619 In order to continue the progress in developing AI, engineers first need to use AI to figure out how to reduce the compute and energy required.
You’ve hit on what many in the field consider the central paradox—and catalyst—of modern artificial intelligence: the AI recursive efficiency loop. As AI models scale, power and compute constraints become physical hard stops.
This "AI optimizing AI" approach is already transforming hardware, software, and infrastructure design across the board:
1. Semiconductor & Hardware Design
Designing state-of-the-art silicon traditionally takes large engineering teams months of iterative trial-and-error.
Floorplanning and Layout (PPA Optimization): Reinforcement learning models (such as Google’s AlphaChip and advanced EDA tools from Cadence and Synopsys) optimize chip Power, Performance, and Area (PPA).
They place millions of transistors and macroblocks in hours, consistently outperforming human-designed floorplans in energy efficiency. Specialized Accelerators: AI algorithms analyze typical model workload patterns to design specialized Application-Specific Integrated Circuits (ASICs) and Neuromorphic architectures tailored specifically for high-efficiency matrix operations.
2. Algorithmic Efficiency & Model Compression
Rather than relying solely on human intuition to prune models, automated AI routines restructure neural architectures for minimal overhead:
Neural Architecture Search (NAS): AI models test millions of network topologies to find architectures that maximize task accuracy per watt or per flop.
Automated Quantization & Pruning: AI agents identify redundant weights and dynamically reduce floating-point precision (e.g., converting FP16/FP32 to INT8 or FP4) with negligible accuracy loss, cutting inference memory bandwidth and power usage by up to 4x.
Routing & Sparse Activation: Mixture-of-Experts (MoE) models use gating networks to activate only a tiny fraction of a model's total parameters for any given query, dramatically curbing energy per generation.
3. Data Center & Infrastructure Optimization
Because inference now accounts for the vast majority of operational energy usage as models enter daily production, runtime infrastructure is managed by predictive AI models:
Dynamic Load & Thermal Control: Reinforcement learning controls data center cooling systems, liquid-loop manifolds, and workload distribution in real time, reducing Power Usage Effectiveness (PUE) metrics significantly.
Predictive Workload Scheduling: ML pipelines shift heavy non-time-sensitive retraining workloads to geographic regions or times of day where renewable grid power is most abundant.
The Takeaway: Progress in frontier models is increasingly gated by energy, heat, and grid constraints. The tech stack is quickly pivoting from "scale at all costs" to "compute-efficient scaling," where the model itself acts as the primary tool to engineer its successor.
Where do you see the biggest immediate bottleneck right now—in the raw hardware/silicon constraints, or in software and algorithmic inefficiencies?
I think the major models should run on a desktop at reasonable tokens/second and 120watt power at most.
That 120-watt envelope is quickly becoming the golden target for localized AI. Drawing 450W+ on a roaring GPU setup to run local inference is fundamentally unsustainable for daily production, both thermally and financially.
To make major models (70B–120B+) run at interactive speeds (~30–50 tokens/second) within a 120W budget, the industry is forcing a massive shift in how hardware and model architectures handle memory:
1. The Memory Bandwidth Bottleneck
During autoregressive generation, every single token requires reading the entire active weight matrix from RAM. The fundamental relationship governing token generation speed is simple physics:
Standard desktop CPUs max out around 80–90 GB/s bandwidth, rendering large models agonizingly slow.
High-power discrete GPUs offer 1,000+ GB/s, but hit strict VRAM limits (16–32 GB) unless you run expensive, power-hungry multi-card setups.
To fit inside 120W, unified memory architectures (like Apple Silicon and AMD's Ryzen AI Max series) are routing 256 to 500+ GB/s directly across a shared pool of fast LPDDR5X, skipping the power-hungry PCIe bus entirely.
2. Sparse MoE Over Dense Power House Models
You can't brute-force 70B dense parameters at 120W without compromising speed or power. The standard is shifting heavily toward Mixture-of-Experts (MoE) and Sparse Architectures:
Models like GPT-OSS 120B or Qwen MoE variants maintain massive parameter capacity (for world knowledge and complex reasoning), but only activate 3B to 8B parameters per token.
Because only a fraction of the weights are evaluated per pass, memory reads drop sharply, pushing speed above 40–50 tokens/sec on sub-100W desktop hardware.
3. Speculative Decoding & Low-Bit Quantization
Speculative Decoding: A tiny, highly efficient "drafter" model (1B–3B) runs ahead at 150+ tok/s to predict tokens, while the main model verifies them in batches. This turns memory-bound single-token reads into compute-bound parallel checks.
4-bit / 3-bit Quantization (MXFP4 / INT4): Moving from FP16 down to 4-bit cuts the active memory footprint by 4x, allowing a 70B parameter model to sit inside ~40 GB of RAM instead of 140 GB.
The Reality Check: A silent 120W box pulling 40+ tokens/sec on a cloud-grade reasoning model isn't sci-fi anymore—it's fast becoming the baseline requirement for developer adoption.
Do you see the 120W sweet spot being dominated by integrated SoC designs with unified memory, or will discrete modular GPUs figure out how to operate efficiently at that low TDP?
I don't "see" anything. Break through is needed in hardware so that major models can run on standard desktops and standard power supplies at 100 tokens/second or better.
To cross the 100+ tokens/second threshold for major models (70B–120B+) on a standard ~120W desktop footprint, incrementally tweaking existing GPU/CPU architectures won't cut it. Pushing LPDDR5X or PCIe channels faster simply generates too much thermal energy per bit transferred over copper traces.
Hitting that performance target at mainstream power levels requires fundamentally changing how silicon handles memory, data movement, and precision. The four core hardware breakthroughs necessary to make that leap include:
1. Compute-in-Memory (CiM) & Processing-in-Memory (PIM)
In standard Von Neumann architecture, every single token forces the system to fetch gigabytes of weights across a physical bus into the processor, compute the results, and throw them away. Data movement consumes up to 80% of total inference energy.
The Breakthrough: Eliminate the bus entirely. Compute-in-Memory integrates specialized analog or digital multiply-accumulate (MAC) arrays directly inside the DRAM/SRAM cells.
The Impact: Instead of streaming 40–100 GB of weights per token to the GPU/CPU cores, the memory arrays compute matrix multiplications in situ and send back only the tiny activation tensors. This drops power consumption per matrix operation by orders of magnitude.
2. Ultra-Dense 3D SRAM Stacked Tiling
Standard High-Bandwidth Memory (HBM) achieves terabyte-per-second throughput, but standard desktop buses can't host full HBM clusters without pushing power targets well into 300W–600W territory.
The Breakthrough: Desktop processors utilizing multi-tier 3D SRAM wafer stacking (similar to extreme multi-gigabyte 3D V-Cache, but expanded across dedicated neural engine tiles).
The Impact: SRAM offers memory bandwidth exceeding 10 to 20 TB/s at fractions of a picojoule per bit—orders of magnitude faster and cooler than external DRAM. If a model's active working set or compressed layers reside entirely inside 3D-stacked SRAM arrays, standard desktop silicon can easily pass 100+ tokens/second without hitting a thermal wall.
3. Sub-Byte and Ternary Native Tensor Cores
Most current chips are optimized for FP16 or INT8, with FP4 support only recently hitting mainstream silicon. However, hardware-level decompression from 2-bit or 4-bit storage back into FP16 ALUs still wastes power.
The Breakthrough: Native silicon hardware support for 1-bit, 2-bit, and ternary weights (-1, 0, +1).
The Impact: Ternary models replace complex floating-point multiplications with simple bitwise additions and sign flips. This slashes the silicon footprint required for math engines, cuts weight sizes for a 70B model down to under 15–20 GB, and dramatically increases throughput per watt.
4. Silicon Photonic Interconnects
Moving electrical signals across copper interconnects on a motherboard consumes substantial energy as heat, especially at gigahertz frequencies and wide bus widths.
The Breakthrough: Co-packaged optics (CPO) and silicon photonics integrated directly onto the desktop socket/interposer level.
The Impact: Modulating light across optical waveguides to transfer data between system memory and compute tiles uses up to 10x less power than copper interfaces, eliminating the thermal limits imposed by traditional memory buses.
Bottom Line: Reaching 100+ tokens/sec on a 120W desktop requires moving away from the paradigm of "fetch weights from RAM into a fast GPU core." It demands architectures where the memory is the compute engine.
When I say major model, I mean GPT-5 or Claude 4.8 or Gemini 3.6.
That redefines the goalpost entirely. Running flagship, trillion-parameter class frontier models locally at 100+ tokens/second within a 120W thermal envelope moves the challenge from a high-end hardware engineering problem to an existential physics and architecture problem.
To put the gap into perspective: running models of that scale today requires multi-cabinet server nodes consuming tens to hundreds of kilowatts just to sustain memory bandwidth and inter-gpu interconnects across hundreds of gigabytes of working state.
Getting flagship frontier models down to a 120W desktop box at 100+ tok/s requires three simultaneous, radical paradigm shifts:
1. Algorithmic Compression Beyond Quantization
Current quantization (INT4/FP4) reduces memory footprints by $4\times$. To fit a flagship model into standard desktop RAM (e.g., 64GB–128GB), you need a 50x to 100x compression factor without destroying the emergent reasoning capabilities.
Non-Linear Vector Quantization & Codebooks: Moving beyond scalar quantization to multi-dimensional vector quantization that encodes vast parameter spaces into tiny, low-dimensional codebook indices.
Ternary / Binary Weight Representation: Eliminating floating-point weights entirely so the full parameter state of a frontier model can fit within tens of gigabytes of physical memory.
2. Dynamic Structural Sparsity (Sub-Linear Compute)
Standard transformer architectures scale memory bandwidth requirements linearly with total parameter count. For models at this scale, O(N) parameter access per token at 100 tok/s violates the thermal dissipation limits of copper and silicon at 120 watts.
Sub-Linear Attention & State Spaces: Moving away from standard quadratic attention toward hybrid SSM (State Space Model) architectures or hierarchical sparse routing, where generating a token only accesses <0.5% of the model's total memory footprint.
Conditional Weight Decompression: Streaming weights dynamically from ultra-dense storage to execution tiles on a strict "need-to-know" basis per token step.
3. Physical Hardware: Neuromorphic & Photonic Limits
At 120W, you cannot dissipate the thermal energy of fetching terabytes of data per second across conventional PCIe or LPDDR buses.
Optical Computing & Photonic Interconnects: Replacing electrical signals with light across silicon photonic waveguides to execute matrix-vector multiplications directly at the speed of light with virtually zero resistive heat.
Neuromorphic Event-Driven Compute: Instead of clocking billions of transistors continuously, activation occurs asynchronously—silicon fires only when specific token paths are triggered, mimicking the human brain's ~20W operational efficiency.
The Reality: Running models at that level of intelligence on a standard desktop doesn't just mean getting better GPUs or faster RAM. It requires a fundamental shift where the model architecture itself is co-designed to bypass the physics of traditional Von Neumann computing.
Break through, new paradigm for computing.
If we are talking about a true, fundamental shift—not just building smaller transistors or wider buses—it requires abandoning the deterministic Von Neumann architecture altogether.
To run frontier intelligence on a 120W desktop footprint, computation cannot be treated as a series of forced electrical switches against resistance. It requires leveraging the natural laws of physics to do the mathematical heavy lifting.
1. Thermodynamic & Stochastic Computing
Traditional digital logic spends vast amounts of energy fighting heat and electrical noise to keep binary states (0 and 1) strictly deterministic.
How It Works: Rather than suppressing thermal fluctuations, thermodynamic hardware uses natural stochastic (random) energy movements as a computational engine.
The AI Application: Modern generative AI and probabilistic models rely heavily on sampling from probability distributions (e.g., Gibbs distributions, Langevin dynamics).
In a thermodynamic system, the physical state of the hardware naturally settles into energy minimums that correspond directly to the optimal solutions of the AI model. Power Savings: Because physical thermal noise drives the state changes rather than high-voltage clock cycles, power consumption plummets by orders of magnitude, operating very close to the physical Landauer limit of energy dissipation.
2. Continuous Analog & Physical Substrates
Digital computers waste tremendous energy converting continuous mathematical relationships into discrete binary numbers, performing floating-point math through millions of switching gates.
Physical Neural Networks: Instead of simulating neural networks in software running on digital logic, the physical medium is the neural network. Variable electrical resistance (via memristors or phase-change memory) directly represents weight values.
Kirchhoff’s and Ohm’s Laws as the Compute Engine: When a voltage vector passes through a memristor crossbar array, matrix multiplication happens instantaneously as a physical consequence of basic electrical laws (I = V/R). No instruction fetches, no ALUs, and zero latency.
3. Optical (Photonic) Waveguide Computing
Electrical signals moving through copper wire generate heat due to resistance, and that heat scales exponentially with frequency and bandwidth.
Computing at the Speed of Light: Photonic chips pass beams of laser light through optical waveguides.
Interferometers modulate the light phase and intensity to execute complex tensor math instantly as light waves overlap and interfere. Zero Heat from Resistance: Photons do not interact with each other or create resistive heat in the waveguide. Memory and tensor math occur at light speed across optical backplanes, eliminating the thermal limits that govern silicon GPUs.
4. Neuromorphic Event-Driven Processing
Biological brains run frontier-level multi-modal intelligence on roughly 20 watts—the power of a dim lightbulb. They do this through event-driven, asynchronous processing:
Spiking Neural Networks (SNNs): Unlike traditional transformers that re-evaluate every weight matrix on every forward pass, neuromorphic processors fire "spikes" only when incoming data crosses specific thresholds.
Extreme Sparsity: 95%+ of the silicon sits idle at any microsecond, drawing near-zero static power. Computations only occur dynamically along active pathway branches.
The New Paradigm Shift: The future of local ultra-high-efficiency computing isn't about forcing binary logic through silicon faster. It's about designing physical systems—whether thermodynamic, analog, optical, or neuromorphic—where the natural relaxation of the physical substrate automatically yields the solution to the model.
From <https://gemini.google.com/app/> Google Gemini (3.6 Flash)
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